Learn VHDL, ISE and FPGA by Designing a basic Home Alarm
English | Size: 2.01 GB
Category: Electronic
This course was designed to equip you with the knowledge and skill that will get you up to speed with FPGA Design in VHDL. You will be expected to have some basic knowledge on digital electronics such as the meaning of Flip Flops, Gates and Finite State Machine, and also some basics of programming language would help in the course.
Although the design flow will be dealt with in almost its entirety, the course starts from the basics and take you up to an intermediate level, where you will be able to take a design from a concept through the different stages of design until seeing the design work on a board.
The course is structured in four parts, starting with a simplistic view at how FPGA’s work and the resources that are available on a typical FPGA. The tool FPGA Editor will be used. Then an overview of ISE Flow will be presented in part 2, along with demos on how the tool is downloaded, installed and used. The third part of the course will explain and demonstrate how the most useful VHDL syntaxes are written, and at each step, the Technology Schematic is viewed to understand how VHDL codes are synthesized into logic.
The last part is about designing a Home Alarm System from the concept and State Diagram. A step-by-step approach is used to show all the stages of the flow, including writing of the codes, Synthesize, add constraints, run Implementation, Timing Analysis, Behavioural Simulation and Post implementation Simulation and Configuration of the FPGA and PROM on a Basys 2 board.
The course consists of 6 hours of videos, spread over 50 lectures, and provide demos to show how the tool is used effectively.
What am I going to get from this course?
Write VHDL Codes
Use FPGA Editor to understand a design and the available resources
Create Testbenches and Run Simulation
Create Timing Constraints
Run Timing Analysis
Add constraints with PlanAhead
View and understand the Technology Schematics after Synthesis
Generate an IP Core
Run Implementation
Extract information from ISE Reports
Solve errors and understand warnings encountered in the ISE flow
Configure the FPGA and ROM with iMPACT
What is the target audience?
The course was designed to help you get started from the basics and rise to an intermediate level
Students
Professionals who want to gain these skills
Electronics Enthusiasts
Research Scientists
About This Course
Published 6/2015 English
Lectures 58
Contents Video: 6 hours
Other: 1.5 hours
Skill Level Intermediate Level
Languages English
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